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NXP Semiconductors /LPC18xx /CREG /CREG5

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Interpret as CREG5

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RESERVED0 (NO_EFFECT)M3TAPSEL 0RESERVED

M3TAPSEL=NO_EFFECT

Description

Chip configuration register 5. Controls JTAG access.

Fields

RESERVED

Reserved.
M3TAPSEL

JTAG debug disable for M3 main processor. If this bit is set to 1, it can be changed to 0 only through a chip reset.

0 (NO_EFFECT): No effect.

1 (DISABLE_JTAG_DEBUG): Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source.
RESERVED

Reserved.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data